(* \nmigen.hierarchy = "test_issuer.ti.core.spr" *) (* generator = "nMigen" *) module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) input coresync_clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) wire [3:0] memory_r_addr; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) wire [63:0] memory_r_data; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) wire [3:0] memory_w_addr; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) wire [63:0] memory_w_data; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) wire memory_w_en; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) reg ren_delay = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) reg \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] spr1__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] \spr1__addr$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] spr1__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [63:0] spr1__data_o; reg [63:0] spr1__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input spr1__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input spr1__wen; reg [63:0] memory [10:0]; initial begin memory[0] = 64'h0000000000000000; memory[1] = 64'h0000000000000000; memory[2] = 64'h0000000000000000; memory[3] = 64'h0000000000000000; memory[4] = 64'h0000000000000000; memory[5] = 64'h0000000000000000; memory[6] = 64'h0000000000000000; memory[7] = 64'h0000000000000000; memory[8] = 64'h0000000000000000; memory[9] = 64'h0000000000000000; memory[10] = 64'h0000000000000000; end reg [3:0] _0_; always @(posedge coresync_clk) begin _0_ <= memory_r_addr; if (memory_w_en) memory[memory_w_addr] <= memory_w_data; end assign memory_r_data = memory[_0_]; always @(posedge coresync_clk) ren_delay <= \ren_delay$next ; always @* begin if (\initial ) begin end \ren_delay$next = spr1__ren; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; endcase end always @* begin if (\initial ) begin end spr1__data_o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) casez (ren_delay) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ 1'h1: spr1__data_o = memory_r_data; endcase end assign memory_w_data = spr1__data_i; assign memory_w_en = spr1__wen; assign memory_w_addr = \spr1__addr$1 ; assign memory_r_addr = spr1__addr; endmodule