diff --git a/nmigen-type-annotations b/nmigen-type-annotations
--- a/nmigen-type-annotations
+++ b/nmigen-type-annotations
@@ -1 +1 @@
-Subproject commit 227f39952a4529cea7f5da76c361bf6b650adff3
+Subproject commit 227f39952a4529cea7f5da76c361bf6b650adff3-dirty
diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 800c7f2a..911bf6ec 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -107,8 +107,8 @@ class FSMMMUStage(ControlBase):
         comb += spr.eq(decode_spr_num(x_fields.SPR))
 
         # based on MSR bits, set priv and virt mode.  TODO: 32-bit mode
-        comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
-        comb += d_in.virt_mode.eq(msr_i[MSR.DR])
+        # comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
+        # comb += d_in.virt_mode.eq(msr_i[MSR.DR])
         #comb += d_in.mode_32bit.eq(msr_i[MSR.SF]) # ?? err
 
         # ok so we have to "pulse" the MMU (or dcache) rather than
@@ -145,10 +145,10 @@ class FSMMMUStage(ControlBase):
                     with m.If(~spr[9] & ~spr[5]):
                         comb += self.debug0.eq(3)
                         #if matched update local cached value
-                        with m.If(spr[0]):
-                            sync += dsisr.eq(a_i[:32])
-                        with m.Else():
-                            sync += dar.eq(a_i)
+                        #with m.If(spr[0]):
+                            #sync += dsisr.eq(a_i[:32])
+                        #with m.Else():
+                            #sync += dar.eq(a_i)
                         comb += done.eq(1)
                     # pass it over to the MMU instead
                     with m.Else():
diff --git a/src/soc/litex/florent b/src/soc/litex/florent
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit 42f7357660b245c4491297d24eebc28b4ac2c21f
+Subproject commit 42f7357660b245c4491297d24eebc28b4ac2c21f-dirty
diff --git a/src/soc/soc-cocotb-sim b/src/soc/soc-cocotb-sim
--- a/src/soc/soc-cocotb-sim
+++ b/src/soc/soc-cocotb-sim
@@ -1 +1 @@
-Subproject commit 25e5b98b796402abc482241775bfe727c9d0a22e
+Subproject commit 25e5b98b796402abc482241775bfe727c9d0a22e-dirty