Libre-SOC Workflow
JTAG TAP DMI XICS
Test Issuer
LS180
nMigen
Verilog libreSOC.v
Settings.pydoDesign.py
Yosis
Verilog ls180.v
LitexPeripherals
LS180Pinmux
YosysBLIF
FlexLibCell Library
YosysBLIF
Next pnrECP 5
ECP 5Cell Structure
Bitstream
ECPS
AllianceVHDL
SPICENetlist
AllianceVHDL (PnR)
GDS II
Coriolis2ASIC
PnR
FPGA